Volatile programmable devices, such as FPGAs, typically rely on non-volatile external storage media to hold the bitstreams used to configure the devices. For example, programmable read-only memory (PROM) devices are often used to hold the configuration bitstreams for FPGAs. Such devices are referred to as “boot PROMs,” because they are used to boot (i.e., initialize) programmable devices, such as volatile FPGAs. A boot PROM device is first programmed with a data pattern in the form of a bitstream corresponding to the desired FPGA configuration, which is typically achieved using an off-board stand-alone programming device, although it is often preferable to program the PROM on-board or in-system.
On-board PROM programming is typically performed using a JTAG interface, which is adapted to communicate with devices compliant with the Joint Test Action Group (JTAG) EEE 1149.1 standard, which governs in-system flash programming. Hence, the term “JTAG” is used with reference both to the standard itself and to devices that are compliant with the standard, which are referred to simply as “JTAG devices.”
However, most memory devices that are commonly used as boot PROMs do not comply with the JTAG standard and thus typically require off-board programming. These devices include, e.g., flash memory devices having a Serial Peripheral Interface (SPI) interface. As understood by those skilled in the art, the term “SPI” indicates compliance with the Serial Peripheral Interface industry bus standard specified by Motorola Corporation of Schaumburg, Ill.
FIG. 1 illustrates a first conventional architecture 110 for using an FPGA 112 to program a JTAG-noncompliant boot PROM 120 having a SPI interface 114. FPGA 112 includes an on-chip JTAG interface 116 (often referred to as a “JTAG engine” or as a “Test Access Port (TAP) controller”) and an on-chip SPI interface 118. SPI interface 118 of FPGA 112 is connected to a SPI interface 114 of a boot PROM 120. In the configuration shown, two headers 122, 124 are provided. The first header is a JTAG header 122 connected to JTAG interface 116 and is used during normal operation of FPGA 112 to send data to and receive data from an external device (not shown) attached to JTAG header 122. The second header is a SPI header 124 connected to SPI interfaces 118 and 114 and is used to program boot PROM 120 by means of an external device (not shown) coupled to SPI header 124. This configuration permits three modes of operation: (1) programming boot PROM 120 using an external device attached to SPI header 124; (2) using programmed boot PROM 120 to program FPGA 112; and (3) normal operation of FPGA 112. This approach involves the board space and fabrication cost of providing two different headers involving two different sets of operations.
FIG. 2 illustrates a second conventional architecture 210 for using an FPGA 212 to program a JTAG-noncompliant boot PROM 220 having a SPI interface 214. FPGA 212 includes an on-chip JTAG interface 216 and an on-chip SPI interface 218. SPI interface 218 of FPGA 212 is connected to a SPI interface 214 of a boot PROM 220. In the configuration shown, a JTAG header 222 is connected to JTAG interface 216 and is used during normal operation of FPGA 212 to send data to and receive data from an external device (not shown) attached to JTAG header 222. JTAG interface 216 and SPI interface 218 are not electrically connected to one another until FPGA 212 has been programmed to make such internal connections, as illustrated graphically by the broken lines in region 226. This configuration permits three modes of operation: (1)(a) first programming boot PROM 220 using an external device (not shown) coupled to JTAG header 222 to pre-program FPGA 212, thereby forming the internal connections shown in region 226, and then (b) using the external device attached to JTAG header 222 to program boot PROM 220 via the internal connections to SPI interface 218; (2) using boot PROM 220 to program FPGA 212; and (3) normal operation of FPGA 212. The two-step approach for programming boot PROM 220 complicates the programming process, thereby increasing cost. Further, programming an FPGA through a JTAG interface is costly in terms of vector size and time, due to increased fuse counts. Additionally, the cost of pre-programming an FPGA device becomes prohibitive when a large volume of on-board production programming of the boot PROM is done on automated testing equipment (ATE). Moreover, this two-step programming approach complicates the process of performing field upgrades to the boot PROM, because the system has to be shut down first to pre-program the FPGA, i.e., background field upgrade of the FPGA is not practical.